Many integrated circuits include a clock circuit for generating a clock signal. In some integrated circuits, the clock circuit includes a phase-lock loop for generating the clock signal based on a reference clock signal. In operation, the phase-lock loop generates a feedback clock signal by dividing a frequency of the clock signal and locks a phase and frequency of the feedback clock signal to a phase and frequency of the reference clock signal. Typically, operation of the phase-lock loop is tested along with the integrated circuit during manufacture of the integrated circuit. One type of test performed on the phase-lock loop determines whether the phase-lock loop operates properly over a specified bandwidth of the clock circuit including the phase-lock loop.
In one technique for testing a bandwidth of a clock circuit including a phase-lock loop, a programmable tester generates a test pattern for generating a reference clock signal at a specified frequency and determines whether the clock signal generated by the phase-lock loop is locked to the reference clock signal. If the clock signal generated by the phase-lock loop is locked to the reference clock signal, the tester generates additional test patterns for changing the phase of the reference clock signal and determines the bandwidth of the phase-lock loop based on phase differences between the output clock signal and the reference clock signal.
Although the technique of generating test patterns to change the phase of the reference clock signal has been successfully employed to measure bandwidths of clocks circuits, some integrated circuit manufacturers do not have access to a tester that is programmable to generate the test patterns required in this technique. In light of the above, a need exists for an improved method of testing a bandwidth of clock circuit. A further need exists for testing a bandwidth of a clock circuit including a phase-lock loop.